1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor memory apparatus, and more particularly, to a level shifting circuit and a nonvolatile semiconductor memory apparatus using the same.
2. Related Art
FIG. 1 is a diagram showing a configuration of a nonvolatile semiconductor memory apparatus of related art. A nonvolatile memory apparatus may comprise, as shown in FIG. 1, a first level shifter 10, a first switching unit 20, a second level shifter 30, and a second switching unit 40.
The first level shifter 10 generates a first shifting signal en1_ls with a level of a pumping voltage VPP when a first enable signal en1 is enabled, and generates the first shifting signal en1_ls with a level of a ground voltage VSS when the first enable signal en1 is disabled.
The first switching unit 20 is turned on when the first shifting signal en1_ls is enabled to the level of the pumping voltage VPP and transfers a program voltage V_pgm to a word line WL. The first switching unit 20 intercepts the transfer of the program voltage V_pgm to the word line WL when the first shifting signal en1_ls is disabled to the level of the ground voltage VSS.
The second level shifter 30 generates a second shifting signal en2_ls with the level of the pumping voltage VPP when a second enable signal en2 is enabled, and generates the second shifting signal en2_ls with the level of the ground voltage VSS when the second enable signal en2 is disabled.
The second switching unit 40 is turned on when the second shifting signal en2_ls is enabled to the level of the pumping voltage VPP and transfers a pass voltage V_pass to the word line WL. The second switching unit 40 intercepts the transfer of the pass voltage V_pass to the word line WL when the second shifting signal en2_ls is disabled to the level of the ground voltage VSS.
The program voltage V_pgm is a voltage for enabling the word line WL, and memory cells connected to the word line WL are programmed when the word line WL is enabled to the level of the program voltage V_pgm. A word line (not shown), which is most adjacent to the word line WL enabled to the level of the program voltage V_pgm, is designed to be applied with the pass voltage V_pass. This is to prevent the occurrence of programming defects due to a coupling phenomenon between the word line WL with a voltage level raised to the level of the program voltage V_pgm and the word line not applied with the program voltage V_pgm.
The first level shifter 10 and the second level shifter 30 have the same configuration except for the different input signals en1 and en2 and the different output signals en1_ls and en2_ls. Therefore, the explanation for the configuration of the first level shifter 10 also applies to the configuration of the second level shifter 30.
FIG. 2 is a diagram showing a configuration of the typical first level shifter 10 of the related art shown in FIG. 1. Referring to FIG. 2, the first level shifter 10 includes first through eighth transistors P1 through P6, N1 and N2, and first and second inverters IV1 and IV2.
In the first level shifter 10, if the first enable signal en1 is enabled to a high level, the eighth transistor N2 is turned on and consequently turns on the second transistor P2. When the second transistor P2 is turned on, the pumping voltage VPP is outputted through the first through third transistors P1 through P3 as the voltage level of the first shifting signal en1_ls.
In the first level shifter 10, if the first enable signal en1 is disabled to a low level, the seventh transistor N1 is turned on, and the ground voltage VSS is outputted as the voltage level of the first shifting signal en1_ls.
Despite that the first level shifter 10 and the second level shifter 30 perform the same function of level-shifting the enable voltage levels of the enable signals en1 and en2 inputted thereto to the level of the pumping voltage VPP, both are designed to be present in the nonvolatile semiconductor memory apparatus.